INL Cluster

Dirac cold-source transistor technologies towards attojoule switching

Global energy demand for information and communication technologies may reach up to 20% of total energy by the end of the decade. Innovations on transistor technologies, following Moore’s law, can in part compensate for this rise and improve sustainability by providing more energy-efficient electronics. However, the energy-efficiency of CMOS is limited by the Boltzmann physics, which sets a lower bound on the operating voltage, and thereby the power. To sustain miniaturization, and improved performance of electronics, new transistor technologies are needed that can overcome this limit.
AttoSwitch will develop a novel cold-source transistor technology that uses the intrinsically cold carrier distribution of Dirac semimetals to overcome the Boltzmann limit. The main objective is to develop a scalable Dirac transistor technology based on largearea integration of 2D and 3D Dirac materials, e.g. graphene and CoSi, and the realization of high-performance device demonstrators at technologically relevant length scales. Key demonstrators are based on graphene integrated with MoS2 and WSe2 channels, as well as novel work on 3D Dirac semimetals. Our methodology includes development of device process modules and extensive material and device characterization. Systematic modeling using new simulation frameworks plays a key part to benchmark and provide a road map for the technology. Our ambitious performance targets include a subthreshold swing of 35 mV/decade and a switching energy of 4 attojoule.
The project links to ongoing European efforts, such as the 2D-experimental pilot line, and the goals set by the European Chips Act. AttoSwitch will impact the semiconductor supply chain at the technology and materials levels, and provide ultra-energy-efficient transistors for logic and high-frequency analog integrated chip markets. Outreach to students, training of young researchers and building international cooperation will also support Europe’s competitiveness in semiconductors.

Total Eligible Budget

3,884,248.50 €

INL Eligible Budget

543,781.25 €

Total Funding

3,884,248.50 €

INL Funding

543,781.25 €

Start Date


End Date


Type of action

RIA Research and Innovation action

Grant Agreement Id



CL4 – Digital, Industry and Space

Funding Framework


INL Role


Approval Date


Main Objective

Pillar II – Global Challenges & European Industrial Competitiveness